1. Technical Field
The present teaching relates generally to methods and systems for analog circuits. More specifically, the present teaching relates to methods and systems for analog to digital converter and systems incorporating the same.
2. Discussion of Technical Background
An analog to digital converter (ADC) is a widely used technology. In a circuit implementing an ADC, the analog input voltage is typically sampled and the quality of an ADC depends on the quality of voltage sampling at the input of the ADC. FIG. 1 shows a typical measurement of VS (110) using an ADC 140. A source resistance RS 120 usually accompanies VS and can be deliberately large in many situations. For example, such an ADC can be measuring the voltage in a Wheatstone bridge, and the resistors in the bridge can have large values. As another example, in certain applications, it may be desired to filter out the high-frequency components into the ADC by introducing an RC filter at the ADC input.
When IIN exists, it causes a voltage drop ΔV 130 across the source resistor 120. In this case, the voltage measured by the ADC will be VS−ΔV rather than VS. Thus, the input current IIN introduces an error into the measurement of the source voltage.
Efforts have been made to reduce such problem. For example, some prior solution introduced a buffer before an ADC and made the buffer's input impedance extremely high. There are several disadvantages to this approach, however. First, a buffer is an extra component, adding cost, size and power dissipation. Second, since no electronic device is perfect, the buffer inevitably introduces noise and distortion into the signal. Third, a buffer only works correctly in a limited voltage range. While the ADC can be designed for input voltages all the way to the supply rails, the introduction of a buffer either limits the input voltage range or requires an additional power supply for the buffer.
Other embedded approaches have been adopted to minimize the input current. To understand how such approaches work, one needs to understand the basic mechanism causing ADC input current. This is shown in FIG. 2 (PRIOR ART). The first part of an ADC 200 performs a function called sample-and-hold, which samples the input voltage 200 to obtain V1 (240) and then stores the sampled voltage V1 (240) on a capacitor C1 250. The sampling is done by turning switch S1 230 on, and the charge is held by closing switch S1 230. If the sampled voltage V1 (240) on capacitor C1 250 is different from VS, there is an associated charge transferred from the input to the ADC, which is C1(VS−V1). If this charge transfer happens with a frequency f, the average input current is f*C1(VS−V1).
Traditionally, the input current can be minimized by pre-charging V1 to VIN before switch S1 is turned on. Different approaches have been used to pre-charge C1 to VIN. One example method, as shown in FIG. 3 (PRIOR ART), is that an ADC 310 uses a unity-gain buffer 320 at the input to charge C1 360. Before S1 330 is turned on, S2 340 is turned on first and then turned off, pre-charging C1 360 so that V1 (350)=VIN. The unity-gain buffer 320 can be designed to have a high input impedance. Unfortunately, when the input is close to the supply rails, the unity-gain buffer 320 can not accurately reproduce VIN at the output of the buffer. Because of this, when it is close to the supply rails, input current still exists.
Another approach of pre-charging is disclosed in U.S. Pat. No. 7,088,280. This approach is described in FIG. 4 (PRIOR ART). With this approach, feedback from a 1-bit ADC is adopted to keep V1 (470), on average, equal to VIN (430). If VIN=f*VREF+, and assuming an accurate ADC, then for a fraction f of the total samples C1 (480) is pre-charged to VREF+ by turning on switch S2 450, while the remainder (1−f) of the time C1 480 is pre-charged to VREF−=0 by turning on switch S3 460. In this case, on average, C1 480 is charged to f*VREF+. When the voltage on C1 (480) is pre-charged to an average of VIN, switch S1 440 can be turned on. At that time, because on average V1=VIN, there will be no input current.
Although this input current cancellation scheme works all the way to the supply rails, due to non-idealities in the switches, the method described in U.S. Pat. No. 7,088,280 does not completely cancel out the undesirable input current. Switches S1 440, S2 450, and S3 460 are typically composed of MOS transistors. It is well known that these transistors suffer from device capacitances and charge injection. Both charge injection and device capacitance are nonlinear functions of the voltage on the MOS terminals. Furthermore, charge injection is very difficult to model correctly. There is no guarantee that the average input current generated under these effects can be canceled out. Therefore, there is a need for a method and system that can pre-charge C1 to a voltage level substantially close to VIN before S1 is turned on, while allowing a full rail-to-rail operation in an ADC circuit.